宁宁-电子科技大学教授-中文百科全书

研究领域

一、研究领域简介

主要从事ADC/DAC数模混合积体电路与系统设计、高速时钟和数据接口电路设计，电源管理积体电路设计等领域的研究工作工作，特别在超高速、高速高精度、低压低功耗ADC和显示驱动等领域有一定成果积累。

二、研究方向

研究内容1：数模混合积体电路与系统设计

（1）新型系统架构设计和ADC/DAC自动校正算法研究。

（2）高速高精度、低压低功耗数模混合积体电路设计技术。

研究内容2：高速时钟和数据接口电路设计

（1）高速锁相环、延迟锁相环、时钟接收等时钟电路研究。

（2）MIPI、LVDS、CML等高速数据输入输出接口电路设计技术。

研究内容3：电源管理积体电路设计

（1）新型数模混合、软硬体协同电源驱动技术研究。

（2）显示驱动、绿色照明、电源管理等领域的积体电路设计开发。

三、承担参与的科研项目情况

先后主持或主研参与了国家973项目子专题1项、国家自然科学基金面上项目1项、部级预先研究项目2项、教育部中央高校基金重大培育项目1项、教育部博士点基金1项、广东省战略新兴产业化项目2项以及多项横向合作项目等，共10余项科研项目。成果转让1项。

学术成果

代表性期刊论文

[1] Jing Li,Shuangyi Wu,Yang Liu,Ning Ning, Qi Yu.A Digital Timing Mismatch Calibration Technique in Time-Interleaved ADCs,IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, 2014, 61(7):486-490.

[2]Ling Du,Ning Ning*,Shuangyi Wu,Qi Yu, Yang Liu. A digital background calibration technique for SAR ADC based on capacitor swapping,IEICE Electronics Express, 2014, 11(12):1-11.

[3]Ning Ning*, Zhenxiao Tong, Dejun Yu, Shuangyi Wu, Wenbin Chen, and Chunyi Feng. “Highly AC Voltage Fluctuation-Resistant LED Driver with Sinusoid-Like reference”,Journal of Power Electronics, 2014, 14(2): 257-264.

[4]Ning Ning*, Zhiling Sui, Jing Li, Shuangyi Wu, Hua Chen, Shuangheng Xu, Qi Yu. “Multi Scaling Coefficients Technique for Convergence Speed Boosting in Gain Error Background Calibration of Pipelined ADC”,Journal of Circuits, System, and Computers, 2014, 23(3), pp: 145003401-145003412.

[5]Ning Ning*, Siyuan Zhao, Kejun Wu, Shuangyi Wu, Taizhong Liu, Junming Han, Liang Li. “A Subthreshold MOSFET Voltage Reference Based on Current Mirror Technology Under 55 nm CMOS Process”,Nanoscience and Nanotechnology Letters, 2014, 6(2), pp:128-133.

[6]Ning Ning*,Ling Du, Hua Chen, Shuangyi Wu, Qi Yu, Yang Liu. “A Dithering Technique for SHA_Less Pipelined ADC”,Journal of Circuits, System, and Computers, 2014, 23(1), pp:14500601-14500612.

[7]Ning Ning*, Wenbin Chen, Dejun Yu, Chunyi Feng, Chengbi Wang. “Self-adaptive load technology for multiplestring LED drivers”,Electronics Letters, 2013, 49(18), pp:1170-1171.

[8]Ling Du,Ning Ning*, Jun Zhang, Qi Yu , Yang Liu. “Self-Calibrated SAR ADC Based on Split Capacitor DAC without use of Fractional Value Capacitor”,IEEJ Transactions on Electrical and Electronic Engineering, 2013, 8(4), pp:408-414.

[9]Ning Ning*, Chunyi Feng, Zhentao Xu, Shuangyi Wu, Kejun Wu, Rui Luo, Qi Yu. “A Sub-1 V Bandgap Reference Based on Different Threshold MOSFETs Under 40 nm Process”,Nanoscience and Nanotechnology Letters, 2012,4(9), pp:919-923.

[10]Ning Ning*, Chunyi Feng, Zhentao Xu, Shuangyi Wu, Kejun Wu, Rui Luo, Qi Yu. “A Sub-1 V Bandgap Reference Based on Different Threshold MOSFETs Under 40 nm Process”,Nanoscience and Nanotechnology Letters, 2012, 4(9): 919-923.

[11]Ning Ning*, Sui Zhiling, Chen Hua, Xu Shuangheng, Jun Zhang, Jie Zheng, Shuangyi Wu, Qi Yu. “Transfer characteristic shift technique for full input range in pipelined ADCs with background calibration”,Electrical Review,2012, 11a: 214-217.

[12]Ning Ning*, Yang Fan, Zhiling Sui, Yingshuai Cao, Shuangyi Wu, Qi Yu. “A Fully Differential Operational Transconductance Amplifier under 40nm CMOS Logic Process”,Nanoscience and Nanotechnology Letters, 2012, 4(8): 849-853.

[13]Jing Li,Ning Ning, Ling Du, Qi Yu, Yang Liu. “The Impact of Gate Leakage Current on PLL in 65nm Technology: Analysis and Optimization”,Journal of Semiconductor technology and Science, 2012, 12(1): 99-106.

[14]Ning Ning*, Yu Qi, Wang Xiang-zhan, Yang Mo-hua, Liu Yuan, Dai Guang-hao. “Settling State Optimization for Folded-Cascode OTA with a Novel Compensation Strategy”.Chinese Journal of Electronics, 2007, 16(1): 63-65.

[15]Ning Ning*, WU Shuang-yi, WANG Xiang-zhan, YANG Mo-hua. “A Novel Power Optimization Method by Minimum Comparator Number Algorithm for Pipeline ADCs”.Journal of Electronic Science and Technology of China, 2007, 5(1): 75-80.

[16]Ning Ning*, Yu Qi, Wang Xiangzhan, Dai Guanghao, Liu Yuan, Yang Mohua. “A Novel Clock Feedthrough Frequency Compensation for Fast-Settling of Folded-Cascode OTA”.Chinese Journal of Semiconductors, 2006, 27(10): 1737-1741.

代表性会议论文

[1]Ling Du,Shuangyi Wu,Min Jiang,Ning Ning,Qi Yu, Yang Liu.A 10-bit 100MS/s Subrange SAR ADC with Time-Domain Quantization,ISCAS2014（国际A类会议）,Melbourne, June 2014.

[2]Shuangyi Wu,Ling Du, Min Jiang,Ning Ning, Qi Yu, Yang Liu.“A 10-bit 100MS/s Time Domain Flash-SAR ADC”,EDSSC2014, Chengdu, June 2014.

[3]Ning Ning,Yong Hu, Jing Li, Chang Yang, Shuangyi Wu, Qi Yu. “Design of a four phase 25% duty cycle DLL with calibration”,EDSSC2013, Hong Kong, June 2013.

[4]Ning Ning,Zhiling Sui, Jing Li, Shuangyi Wu, Hua Chen, Shuangheng Xu, Qi Yu. “Multi scaling coefficients technique for noisy signal based gain error background calibration”,EDSSC2012, Bangkok Thailand, Dec. 2012.

[5]Jing Li,Ning Ning,Yong Hu, Kejun Wu. “A Low-jitter Low-area PLL with Process-independent Bandwidth”,IEEEICSICT-2012, Xi'an, Oct. 2012.

[6]Ao Qian, Chen Rongguan,Ning Ning, Sun Guozhi, Zhang Xiaochen, Zheng Jie, Kong Deyu. “High-definition Image Processing Algorithm and Digital Platform Design”,CIT2012, Chengdu, Oct. 2012.

[7]Qi Yu, Wen Luo,Ning Ning, Zhenya Sun, Chengbi Wang, Yong Hu, Tianzhu Li. “A CMOS dB-linear Variable Amplifier Using Curve matching”,IEEE MEC 2011, Jilin, Aug. 2011.

[8]Qi Yu, Zhentao.Xu,Ning Ning, Yunchao Guan, Bijiang Chen. “Design of a relaxation oscillator with low power-sensitivity and high temperature-stability”,EEIC 2011, Nanchang, June 2011.

[9]Qi Yu, Zhi Chen,Ning Ning, Hao Liu, Hong Chen, Wandong Zhang. “A High Order Curvature-Compensated Op-Amps-Avoided Bandgap Reference”,IEEE ICSICT-2010, Shanghai, Nov. 2010.

[10]Ning Ning, Long Fan, Shuang-yi Wu, Yuan Liu, Guo-qing Liu, Qi Yu, Mo-hua Yang. “An 8-Bit 250MSPS Modified Two-Step ADC”.IEEE ICCCAS 2nd. Guilin, June 2006.

[11]Qi Yu, Xiang-zhan Wang,Ning Ning, Lin Tang, Hong-Bin Li, Mo-hua Yang. “A 10-Bit 100MSPS 0.35µm Si CMOS Pipeline ADC”,IEEE ICSICT 7th, Beijing, Oct. 2004.

出版刊物

1.《科教结合协同育人行动计画进展报告(2012-2013年)》(高等教育人才培养改革丛书), 高等教育出版社, 2014年8月,ISBN: 978-7-04-040776-1.